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PCA9540B 2-channel I2C multiplexer
Product data sheet Supersedes data of 2004 Apr 13 2004 Sep 29
Philips Semiconductors
Philips Semiconductors
Product data sheet
2-channel I2C multiplexer
PCA9540B
FEATURES
* 1-of-2 bi-directional translating multiplexer * I2C interface logic; compatible with SMBus standards * Channel selection via I2C-bus * Power up with all multiplexer channels deselected * Low RdsON switches * Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and
5 V buses
* No glitch on power-up * Supports hot insertion * Low stand-by current * Operating power supply voltage range of 2.3 V to 5.5 V * 5 V tolerant Inputs * 0 to 400 kHz clock frequency * ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 1000 V per JESD22-C101
PIN CONFIGURATION
SCL SDA VDD SD0
1 2 3 4
8 7 6 5
SC1 SD1 VSS SC0
* Latch-up testing is done to JESDEC Standard JESD78 which
exceeds 100 mA
SW00491
* Packages Offered:
DESCRIPTION
Figure 1. Pin configuration SO8, TSSOP8
PIN DESCRIPTION
PIN NUMBER 1 2 3 4 5 6 7 8 SYMBOL SCL SDA VDD SD0 SC0 VSS SD1 SC1 FUNCTION Serial clock line Serial data line Supply voltage Serial data 0 Serial clock 0 Supply ground Serial data 1 Serial clock 1
The PCA9540B is a 1-of-2 bi-directional translating multiplexer, controlled via the I2C-bus. The SCL/SDA upstream pair fans out to two SCx/SDx downstream pairs, or channels. Only one SCx/SDx channel is selected at a time, determined by the contents of the programmable control register. A power-on reset function puts the registers in their default state and initializes the I2C state machine with no channels selected. The pass gates of the multiplexer are constructed such that the VDD pin can be used to limit the maximum high voltage which will be passed by the PCA9540B. This allows the use of different bus voltages on each SCx/SDx pair, so that 1.8 V, 2.5, or 3.3 V parts can communicate with 5 V parts without any additional protection. External pull-up resistors can pull the bus up to the desired voltage level for this channel. All I/O pins are 5 V tolerant. The PCA9540B has replaced the PCA9540 and all designs must migrate to the PCA9540B. PCA9540B samples can be requested from www.philipslogic.com/products/I2Cmuxes/.
ORDERING INFORMATION
PACKAGES 8-Pin Plastic SO TEMPERATURE RANGE -40 C to +85 C ORDER CODE PCA9540BD TOPSIDE MARK PA9540B DRAWING NUMBER SOT96-1 SOT505-1
8-Pin Plastic TSSOP -40 C to +85 C PCA9540BDP 9540B Standard packing quantities and other packaging data are available at www.standardproducts.philips.com/packaging.
2004 Sep 29
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Philips Semiconductors
Product data sheet
2-channel I2C multiplexer
PCA9540B
BLOCK DIAGRAM
PCA9540B
SD0
SD1
SC0
SC1
SWITCH CONTROL LOGIC VSS
VDD
Power-on Reset
SCL Input Filter SDA I2C-Bus Control
SW02211
Figure 2. Block diagram
2004 Sep 29
3
Philips Semiconductors
Product data sheet
2-channel I2C multiplexer
PCA9540B
DEVICE ADDRESSING
Following a START condition the bus master must output the address of the slave it is accessing. The address of the PCA9540B is shown in Figure 3.
POWER-ON RESET
When power is applied to VDD, an internal Power-On Reset holds the PCA9540B in a reset condition until VDD has reached VPOR. At this point, the reset condition is released and the PCA9540B registers and I2C state machine are initialized to their default states, all zeroes causing all the channels to be deselected. Thereafter, VDD must be lowered below 0.2 V to reset the device.
1
1
1
0
0
0
0
R/W
FIXED
SW00713
VOLTAGE TRANSLATION
The pass gate transistors of the PCA9540B are constructed such that the VDD voltage can be used to limit the maximum voltage that will be passed from one I2C bus to another.
Figure 3. Slave address The last bit of the slave address defines the operation to be performed. When set to logic 1, a read is selected while a logic 0 selects a write operation.
Vpass vs. VDD
CONTROL REGISTER
Following the successful acknowledgement of the slave address, the bus master will send a byte to the PCA9540B which will be stored in the Control Register. If multiple bytes are received by the PCA9540B, it will save the last byte received. This register can be written and read via the I2C bus.
CHANNEL SELECTION BITS (READ/WRITE) 7 X 6 X 5 X 4 X 3 X 2 B2 1 B1 0 B0
5.0 4.5 MAXIMUM 4.0 TYPICAL 3.5 Vpass 3.0 2.5 2.0 1.5 1.0 2.0 2.5 3.0 3.5 4.0 VDD 4.5 5.0 5.5 MINIMUM
ENABLE BIT
SW00839
SW00820
Figure 4. Control register Figure 5. Vpass voltage
CONTROL REGISTER DEFINITION
A SCx/SDx downstream pair, or channel, is selected by the contents of the control register. This register is written after the PCA9540B has been addressed. The 2 LSBs of the control byte are used to determine which channel is to be selected. When a channel is selected, the channel will become active after a stop condition has been placed on the I2C bus. This ensures that all SCx/SDx lines will be in a HIGH state when the channel is made active, so that no false conditions are generated at the time of connection. Table 1. Control Register; Write -- Channel Selection/ Read -- Channel Status D7 X X X X 0 D6 X X X X 0 D5 X X X X 0 D4 X X X X 0 D3 X X X X 0 B2 0 1 1 1 0 B1 X 0 0 1 0 B0 X 0 1 X 0 COMMAND No channel selected Channel 0 enabled Channel 1 enabled No channel selected No channel selected; power-up default state Figure 5 shows the voltage characteristics of the pass gate transistors (note that the graph was generated using the data specified in the DC Characteristics section of this datasheet). In order for the PCA9540B to act as a voltage translator, the Vpass voltage should be equal to, or lower than the lowest bus voltage. For example, if the main bus was running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then Vpass should be equal to or below 2.7 V to effectively clamp the downstream bus voltages. Looking at Figure 5, we see that Vpass (max.) will be at 2.7 V when the PCA9540B supply voltage is 3.5 V or lower so the PCA9540B supply voltage could be set to 3.3 V. Pull-up resistors can then be used to bring the bus voltages to their appropriate levels (see Figure 12). More Information can be found in Application Note AN262 PCA954X family of I 2C/SMBus multiplexers and switches.
2004 Sep 29
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Philips Semiconductors
Product data sheet
2-channel I2C multiplexer
PCA9540B
CHARACTERISTICS OF THE I2C-BUS
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P) (see Figure 7).
Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see FIgure 6).
System configuration
A device generating a message is a `transmitter', a device receiving is the `receiver'. The device that controls the message is the `master' and the devices which are controlled by the master are the `slaves' (see Figure 8).
SDA
SCL data line stable; data valid change of data allowed
SW00363
Figure 6. Bit transfer
SDA
SDA
SCL S START condition P STOP condition
SCL
SW00365
Figure 7. Definition of start and stop conditions
SDA SCL
MASTER TRANSMITTER/ RECEIVER
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
I2C MULTIPLEXER
SLAVE
SW00366
Figure 8. System configuration
2004 Sep 29
5
Philips Semiconductors
Product data sheet
2-channel I2C multiplexer
PCA9540B
Acknowledge
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START condition 1 2 8 9 clock pulse for acknowledgement
SW00368
Figure 9. Acknowledgement on the
I2C-bus
SLAVE ADDRESS
CONTROL REGISTER
SDA
S
1
1
1
0
0
0
0
0 R/W
A
X
X
X
X
X
B2
B1
B0
A
P
start condition
acknowledge from slave
acknowledge from slave
SW00800
Figure 10. WRITE control register
SLAVE ADDRESS
CONTROL REGISTER
last byte
SDA
S
1
1
1
0
0
0
0
1 R/W
A
X
X
X
X
X
B2
B1
B0
NA
P stop condition
start condition
acknowledge from slave
no acknowledge from master
SW00499
Figure 11. READ control register
2004 Sep 29
6
Philips Semiconductors
Product data sheet
2-channel I2C multiplexer
PCA9540B
TYPICAL APPLICATION
VDD = 2.7 - 5.5 V VDD = 3.3 V V = 2.7 - 5.5 V
SDA SCL
SDA SCL
SD0 CHANNEL 0 SC0
V = 2.7 - 5.5 V
I2C/SMBus MASTER SD1 CHANNEL 1 SC1 VSS
PCA9540B
SW02212
Figure 12. Typical application
2004 Sep 29
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Philips Semiconductors
Product data sheet
2-channel I2C multiplexer
PCA9540B
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134).Voltages are referenced to GND (ground = 0 V). SYMBOL VDD VI II IO IDD ISS Ptot Tstg Tamb PARAMETER DC supply voltage DC input voltage DC input current DC output current Supply current Supply current total power dissipation Storage temperature range Operating ambient temperature CONDITIONS RATING -0.5 to +7.0 -0.5 to +7.0 20 25 100 100 400 -60 to +150 -40 to +85 UNIT V V mA mA mA mA mW C C
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C.
DC CHARACTERISTICS
SYMBOL Supply VDD IDD Istb VPOR VIL VIH IO OL IL Ci Pass Gate RO ON Supply voltage Supply current Standby current
VDD = 2.3 to 3.6 V; VSS = 0 V; Tamb = -40 to +85 C; unless otherwise specified. (See page 9 for VDD = 3.6 to 5.5 V) PARAMETER TEST CONDITIONS LIMITS MIN 2.3 Operating mode; VDD = 3.6 V; no load; VI = VDD or VSS; fSCL = 100 kHz Standby mode; VDD = 3.6 V; no load; VI = VDD or VSS; fSLC = 0 kHz no load; VI = VDD or VSS -- -- -- -0.5 0.7VDD VOL = 0.4 V VOL = 0.6 V VI = VDD or VSS VI = VSS VCC = 3.0 to 3.6 V, VO = 0.4 V, IO = 15 mA VCC = 2.3 to 2.7 V, VO = 0.4 V, IO = 10 mA Vswin = VDD = 3.3 V; Iswout = -100 A VPass Switch output voltage Vswin = VDD = 3.0 to 3.6 V; Iswout = -100 A Vswin = VDD = 2.5 V; Iswout = -100 A Vswin = VDD = 2.3 to 2.7 V; Iswout = -100 A IL Cio Leakage current Input/output capacitance VI = VDD or VSS VI = VSS 3 6 -1 -- 5 7 -- 1.6 -- 1.1 -1 -- TYP -- 20 0.1 1.6 -- -- -- -- -- 7 11 16 1.9 -- 1.5 -- -- 2.5 MAX 3.6 50 1 2.1 0.3VDD 6 -- -- +1 8 31 55 -- 2.8 -- 2.0 +1 5 A pF V UNIT
V A A V V V mA mA A pF
Power-on reset voltage (Note 1) LOW-level input voltage HIGH-level input voltage LOW-level LOW level output current Leakage current Input capacitance
Input SCL; input/output SDA
Switch resistance
NOTE: 1. VDD must be lowered to 0.2 V in order to reset part.
2004 Sep 29
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Philips Semiconductors
Product data sheet
2-channel I2C multiplexer
PCA9540B
DC CHARACTERISTICS
SYMBOL Supply VDD IDD Istb VPOR1 VIL VIH IO OL IIL IIH Ci Pass Gate RON VPass IL Cio
VDD = 3.6 to 5.5 V; VSS = 0 V; Tamb = -40 to +85 C; unless otherwise specified. (See page 8 for VDD = 2.3 to 3.6 V) PARAMETER TEST CONDITIONS LIMITS MIN 3.6 Operating mode; VDD = 5.5 V; no load; VI = VDD or VSS; fSCL = 100 kHz Standby mode; VDD = 5.5 V; no load; VI = VDD or VSS no load; VI = VDD or VSS -- -- -- -0.5 0.7 VDD VOL = 0.4 V VOL = 0.6 V VI = VSS VI = VDD VI = VSS VCC = 4.5 to 5.5 V, VO = 0.4 V, IO = 15 mA Vswin = VDD = 5.0 V; Iswout = -100 A Vswin = VDD = 4.5 to 5.5 V; Iswout = -100 A VI = VDD or VSS VI = VSS 3 6 -1 -1 -- 4 -- 2.6 -1 -- TYP -- 65 0.3 1.6 -- -- -- -- -- -- 6 9 3.6 -- -- 2.5 MAX 5.5 100 1 2.1 0.3 VDD 6 -- -- 1 1 8 24 -- 4.5 +1 5 UNIT
Supply voltage Supply current Standby current Power-on reset voltage LOW-level input voltage HIGH-level input voltage LOW-level LOW level output current LOW-level input current HIGH-level input current Input capacitance Switch resistance Switch output voltage Leakage current Input/output capacitance
V A A V V V mA A mA A pF V V A pF
Input SCL; input/output SDA
NOTE: 1. VDD must be lowered to 0.2 V in order to reset part.
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Philips Semiconductors
Product data sheet
2-channel I2C multiplexer
PCA9540B
AC CHARACTERISTICS
SYMBOL tpd fSCL tBUF tHD;STA tLOW tHIGH tSU;STA tSU;STO tHD;DAT tSU;DAT tR tF Cb tSP tVD:DATL tVD:DATH tVD:ACK PARAMETER Propagation delay from SDA to SDn or SCL to SCn SCL clock frequency Bus free time between a STOP and START condition Hold time (repeated) START condition After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Set-up time for STOP condition Data hold time Data set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Capacitive load for each bus line Pulse width of spikes which must be suppressed by the input filter Data valid (HL)4 Data valid (LH)4 Data valid Acknowledge STANDARD-MODE I2C-BUS MIN -- 0 4.7 4.0 4.7 4.0 4.7 4.0 02 250 -- -- -- -- -- -- -- MAX 0.31 100 -- -- -- -- -- -- 3.45 -- 1000 300 400 50 1 0.6 1 FAST-MODE I2C-BUS MIN -- 0 1.3 0.6 1.3 0.6 0.6 0.6 02 100 20 + 0.1Cb3 20 + 0.1Cb3 -- -- -- -- -- MAX 0.31 400 -- -- -- -- -- -- 0.9 -- 300 300 400 50 1 0.6 1 ns kHz s s s s s s s ns ns s s ns s s s UNIT
NOTES: 1. Pass gate propagation delay is calculated from the 20 typical RON and and the 15 pF load capacitance. 2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. 3. Cb = total capacitance of one bus line in pF. 4. Measurements taken with 1 k pull-up resistor and 50 pF load.
SDA
tBUF
tLOW
tR
tF
tHD;STA
tSP
SCL
tHD;STA P S tHD;DAT tHIGH tSU;DAT Sr
tSU;STA
tSU;STO P
SU00645
Figure 13. Definition of timing on the
I2C-bus
2004 Sep 29
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Philips Semiconductors
Product data sheet
2-channel I2C multiplexer
PCA9540B
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
2004 Sep 29
11
Philips Semiconductors
Product data sheet
2-channel I2C multiplexer
PCA9540B
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm
SOT505-1
2004 Sep 29
12
Philips Semiconductors
Product data sheet
2-channel I2C multiplexer
PCA9540B
REVISION HISTORY
Rev _2 Date 20040929 Description Product data sheet (9397 750 13731). Supersedes data of 2004 Apr 13 (9397 750 12918). Modifications:
* Section "Control Register Definition" on page 4: add "No channel selected; power-up default state" row to
bottom of Table 1.
* Section "Power-on Reset" on page 4 re-written. * AC characterists table on page 10: Add Note 4 and references to it at parameters tVD;DATL and tVD;DATH.
_1 20040413 Product data (9397 750 12918).
2004 Sep 29
13
Philips Semiconductors
Product data sheet
2-channel I2C multiplexer
PCA9540B
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011.
Data sheet status
Level
I
Data sheet status [1]
Objective data
Product status [2] [3]
Development
Definitions
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data
Qualification
III
Product data
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2004 All rights reserved. Printed in U.S.A. Date of release: 09-04
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document order number:
9397 750 13731
Philips Semiconductors
2004 Sep 29 14

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